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280 Software Developer’s Manual
Register Descriptions
13.4.7.1.22 PHY LED Control Register (82544GC/EI Only)
PLED (24d; R/W)
LED Stretch Disable 11
Disable the SPEED_1000_LED
Extension Logic.
0b = Enable logic.
1b = Disable logic.
Note: Only when both the stretch and
blink are disabled the input bypasses
the blink logic and is muxed out with no
sampling (only combinational logic).
R/W 1b 1b
Reserved 15:12
Always read as 0b. Write to 0b for
normal operation
R/W 00b 00b
Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description
Table 13-46. PHY LED Control Bit Description
Field Bit(s) Description Mode HW Rst SW Rst
LED_TX control 0
1b = Activity/Link.
0b = Transmit activity.
R/W 0b Retain
LED_RX control 1
1b = Receive activity/Link.
0b = Receive activity.
R/W 0b Retain
Reserved 2 Reserved. Should be set to 0b. R/W 0b Retain
LED_LINK control 4:3
1xb = Link[2:1], Link.
01b = Link, Speed[1:0].
00b = Link[2:0].
R/W 00b Retain
Reserved 7:5 Reserved. Should be set to 000b. R/W 000b Retain
Blink Rate 10:8
000b = 42 ms.
001b = 84 ms.
010b = 170 ms.
011b = 340 ms.
100b = 670 ms.
101b to 111b = Reserved.
R/W 001b Retain
Force INT# to Assert 11
0b = Do not force INT# assertion.
1b = Force INT# assertion.
R/W 0b Retain
Pulse stretch duration 14:12
000b = no pulse stretching.
001b = 21 ms to 42 ms.
010b = 42 ms to 84 ms.
01b1 = 84 ms to 170 ms.
100b = 170 ms to 340 ms.
101b = 340 ms to 670 ms.
110b = 670 ms to 1.3 s.
111b = 1.3s to 2.7 s.
R/W 100b Retain
Disable LED 15
0b = Enable.
1b = Disable.
R/W 0b Retain