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IQ80960RM/RN
Evaluation Board Manual 5-3
MON960 Support for IQ80960RM/RN
5.2.5 Primary PCI Interface Initialization
The IQ80960RM/RN platform is a multi-function PCI device. On the primary PCI bus, two
functions (from a PCI Configuration Space standpoint) are supported.
• Function 0 is the PCI-to-PCI Bridge of the i960 RM/RN I/O processor, which optionally
provides access capability between the primary PCI bus and the secondary PCI bus.
• Function 1 is the Primary ATU which provides access capability between the primary PCI bus
and the local i960 bus.
The platform can be initialized into one of four modes. Modes 0 and 3 are described below.
When the IQ80960RM/RN is operating in Mode 0, the processor core is held in reset, allowing
register defaults to be used on the Primary PCI interface. This mode is used to program the onboard
Flash with either IxWORKS* or MON960.
When the IQ80960RM/RN platform is operating in Mode 3, the Configuration Cycle Disable bit in
the Extended Bridge Control Register (EBCR) is set after IQ80960RM/RN processor reset. In this
mode, the IQ80960RM/RN platform sends PCI Retries when the PCI host attempts to access the
platform’s Configuration Space. This mode allows the IQ80960RM/RN processor time to initialize
its internal registers. The processor remains in this mode until the Configuration Cycle Disable bit
in the Extended Bridge Control Register (EBCR) is cleared. For this reason, and to prevent PCI
host problems, Primary PCI initialization occurs at the earliest possible opportunity after Memory
and SDRAM controller initialization.
5.2.6 Primary ATU Initialization
Primary ATU (Bridge) initialization includes initialization by the 80960JT core and initialization
by the PCI host processor. Local initialization occurs first and consists mainly of establishing the
operational parameters for access to the local IQ80960RM/RN platform bus. The Primary Inbound
ATU Limit Register (PIALR) is initialized to establish the block size of memory required by the
Primary ATU. The PIALR value is based on the installed SDRAM configuration. The Primary
Inbound ATU Translate Value Register (PIATVR) is initialized to establish the translation value for
PCI-to-Local accesses. The PIATVR value is set to reference the base of local SDRAM. The
Primary Outbound Memory Window Value Register (POMWVR) is initialized to establish the
translation value for Local-to-PCI accesses. The POMWVR value remains at its default value of
“0” to allow the IQ80960RM/RN platform to access the start of the PCI Memory address map,
which is typically occupied by PCI host memory. Likewise, the Primary Outbound I/O Window
Value Register (POIOWVR) remains at its default value of “0” to allow the IQ80960RM/RN
platform to access the start of the PCI I/O address map. PCI Doorbell-related parameters are also
established to allow for communication between the IQ80960RM/RN platform and a PCI bus
master using the doorbell mechanism.
Table 5-1. Initialization Modes
RST_MODE#/
SW1-1
RETRY/
SW1-2
Initialization
Mode
Primary PCI Interface
i960 Core
Processor
0/ON 0/ON Mode 0 Accepts Transactions Held in Reset
0/ON 1/OFF Mode 1 Retries All Configuration Transactions Held in Reset
1/OFF 0/ON Mode 2 Accepts Transactions Initializes
1/OFF 1/OFF Mode 3 (default) Retries All Configuration Transactions Initializes