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CHAPTER 3
AMI
®
BIOS USERS GUIDE
PCI Frame Buffer USWC
The Pentium
®
II processor supports the Uncacheable Speculatable
Write-Combining (USWC) memory type. The processor provides a write-
combining with buffering strategy for write operation. This is useful for
frame buffering. Writing to USWC memory can be buffered and combined in
the processors write-combining buffer (WCB). The WCBs are viewed as a
special purpose outgoing write buffers, rather than a cache. The WCBs are
written into memory to allocate a different address, or after executing a
serializing, locked, or I/O instructions.
During Enabled, this will enable the processor memory location
C000 and DFFF segment as USWC memory type.
DRAM Refresh Queue
Choose Enabled, the system will provide 4-deep refresh queue. All
refresh request are queued, with the 4th refresh request being the priority
request. All refresh requests are priority when the refresh queue is Disabled.
Fixed Memory Hole
This option allows the end user to specify the location of a memory
hole. The cycle matching the selected memory hole will be passed to the
ISA bus. If Enabled, the selected hole is not remapped.
CPU To PCI IDE Posting
Set this option to Enabled to enable posted messages from the CPU
to the PCI bus or IDE controller. The settings are Enabled or Disabled. The
Optimal and Fail-Safe default settings are Enabled.
USWC Write I/O Post
Set this option to Enabled to use USWC(Uncacheable,
Speculatable, Write-Combined) memory. The settings are Enabled or
Disabled. The Optimal and Fail-Safe default settings are Disabled.
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