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Chapter 4 Award BIOS Setup
PMB-601LF USER
′
S MANUAL
Page: 4-13
CAS LATENCY TIME:
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
DRAM RAS# TO CAS# DELAY:
This item let you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Fast
gives faster performance; and Slow gives more stable performance. This
field applies only when synchronous DRAM is installed in the system.
The choices are 2 and 3.
DRAM RAS# PRECHARGE TIME:
If an insufficient number of cycles is allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the DRAM
may fail to retain data. Fast gives faster performance; and Slow gives more
stable performance. This field applies only when synchronous DRAM is
installed in the system. The choices are 2 & 3.
PRECHARGE DEALY (tRAS):
Precharge Delay This setting controls the precharge delay, which
determines the timing delay for DRAM precharge
SYSTEM MEMORY FREQUENCY:
Allow to choose different frequency of memory module.
MEMORY HOLE AT 15-16M:
You can reserve this area of system memory for ISA adapter ROM. When
this area is reserved, it cannot be cached. The user information of
peripherals that need to use this area of system memory usually discusses their
memory requirements
PEG/ONCHIP VGA CONTROL:
To select the PCI-Express Graphics or onchip VGA Graphics.
ON-CHIP FRAME BUFFER SIZE:
The On-Chip Frame Buffer Size can be set as 32MB. This memory is shared
with the system memory.
DVMT MODE:
Intel Dynamic Video Memory Technology Mode.