Design Considerations (Continued)
TABLE IV Memory Map of HPC167064 Emulating an HPC16083
FFFFFFF0 Interrupt Vectors
FFEFFFD0 JSRP Vectors
FFCFFFCE
On-Chip EPROM
E001E000
( User Memory
DFFFDFFE External Expansion
Memory
02010200 (
01FF01FE
On-Chip RAM User RAM
01C101C0
(
01950194 WATCHDOG Register WATCHDOG Logic
0192 T0CON Register
01910190 TMMODE Register
018F018E DIVBY Register
018D018C T3 Timer
018B018A R3 Register
Timer Block T0T3
01890188 T2 Timer
01870186 R2 Register
01850184 I2CR RegisterR1
01830182 I3CR RegisterT1
01810180 I4CR Register
015E015F EICR
Timer Block T4T7
015C EICON
01530152 Port P Register
01510150 PWMODE Register
014F014E R7 Register
014D014C T7 Timer
014B014A R6 Register
01490148 T6 Timer
01470146 R5 Register
01450144 T5 Timer
01430142 R4 Register
01410140 T4 Timer
0128 ENUR Register
0126 TBUF Register
0124 RBUF Register UART
0122 ENUI Register
0120 ENU Register
0104 Port D Input Register
00F500F4 BFUN Register
PortsAB
00F300F2 DIR B Register
Control
00F100F0 DIR A Register IBUF
00E6 UPIC Register UPI Control
00E300E2 Port B
PortsAB
00E100E0 Port AOBUF
00DE Reserved
00DD00DC HALT Enable Register
Port Control
00D8 Port I Input Register
Interrupt
00D6 SIO Register
Control
00D4 IRCD Register
Registers
00D2 IRPD Register
00D0 ENIR Register
00CF00CE X Register
00CD00CC B Register
00CB00CA K Register
00C900C8 A Register HPC Core
00C700C6 PC Register Registers
00C500C4 SP Register
00C300C2 Reserved
00C0 PSW Register
00BF00BE
On-Chip
RAM
User RAM
00010000
26