E‐14HardwareReferenceManual www.picocomputing.com PicoComputing,Inc.
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RAM_A7 E22 Address7 O SSTL18_II_DCI
RAM_A8 D24 Address8 O SSTL18_II_DCI
RAM_A9 F20 Address9 O SSTL18_II_DCI
RAM_A10 F23 Address10 O SSTL18_II_DCI
RAM_A11 A14 Address11 O SSTL18_II_DCI
RAM_A12 D23 Address12[MSB] O SSTL18_II_DCI
RAM_BA0 E23 BankAddress0 O SSTL18_II_DCI
RAM_BA1 K18 BankAddress1 O SSTL18_II_DCI
RAM_CLK C14 Clock O SSTL18_II_DCI
RAM_CLK F15 ClockFeedback I SSTL18_II_DCI
RAM_CLKE0 A15 ClockEnable0[PowerSaveMode] O SSTL18_II_DCI
RAM_CLKE1 G22 ClockEnable1[PowerSaveMode] O SSTL18_II_DCI
RAM_D0 C19 Data0(LSB) I/O SSTL18_II_DCI
RAM_D1 F18 Data1 I/O SSTL18_II_DCI
RAM_D2 G20 Data2 I/O SSTL18_II_DCI
RAM_D3 D19 Data3 I/O SSTL18_II_DCI
RAM_D4 C21 Data4 I/O SSTL18_II_DCI
RAM_D5 E20 Data5 I/O SSTL18_II_DCI
RAM_D6 F17 Data6 I/O SSTL18_II_DCI
RAM_D7 B17 Data7 I/O SSTL18_II_DCI
RAM_D8 D15 Data8 I/O SSTL18_II_DCI
RAM_D9 D14 Data9 I/O SSTL18_II_DCI
RAM_D10 C16 Data10 I/O SSTL18_II_DCI
RAM_D11 A17 Data11 I/O SSTL18_II_DCI
RAM_D12 G17 Data12 I/O SSTL18_II_DCI
RAM_D13 B16 Data13 I/O SSTL18_II_DCI
RAM_D14 C12 Data14 I/O SSTL18_II_DCI
RAM_D15 B12 Data15 I/O SSTL18_II_DCI
RAM_D16 H19 Data16 I/O SSTL18_II_DCI
RAM_D17 H22 Data17 I/O SSTL18_II_DCI
RAM_D18 G24 Data18 I/O SSTL18_II_DCI
RAM_D19 H24 Data19 I/O SSTL18_II_DCI
RAM_D20 J21 Data20 I/O SSTL18_II_DCI
RAM_D21 G19 Data21 I/O SSTL18_II_DCI
RAM_D22 K20 Data22 I/O SSTL18_II_DCI
RAM_D23 K23 Data23 I/O SSTL18_II_DCI
RAM_D24 M22 Data24 I/O SSTL18_II_DCI
RAM_D25 M24 Data25 I/O SSTL18_II_DCI
RAM_D26 K21 Data26 I/O SSTL18_II_DCI
RAM_D27 L24 Data27 I/O SSTL18_II_DCI
RAM_D28 N22 Data28 I/O SSTL18_II_DCI
RAM_D29 L19 Data29 I/O SSTL18_II_DCI
RAM_D30 N24 Data30 I/O SSTL18_II_DCI
RAM_D31 J23 Data31 I/O SSTL18_II_DCI
RAM_DM0‐7 E17 DataMask[0‐7] O SSTL18_II_DCI
RAM_DM8‐15 C13 DataMask[8‐15] O SSTL18_II_DCI