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When using the channel A DTR/REQ pin for transmit DMA the SCC must be
programmed so that the request release timing of this pin is identical to the WAIT/REQ
timing. This is done by setting bit D4 of write register 7 prime.
NOTE:
Even though the W/REQA pin can be used for both DMA transmit
and DMA receive, obviously it cannot be used for both
simultaneously. Therefore, bits D0 and D1 of the Configuration
Register should never be cleared at the same time while bits D2 and
D3 are both set. This situation may result in damage to the system.
Figure 3 Block Diagram of DMA on MPA-100
W/REQA
DTR/REQA
W/REQB
SCC
DMATRQ
DMARRQ
J8
J9
PAL
MPA-100 User's Manual 7-2