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1. INTRODUCTION
The Quatech MPA-100 is a single channel, synchronous RS-232 compatible serial
communication port for systems utilizing the architecture of the IBM AT personal computer or
compatible. Figure 1 depicts the layout of the MPA-100.
Figure 1 MPA-100 Board Layout
Quatech, Inc.
MPA-100
U1
U2
SW1 SW2
U3
U4
U5
U6
U7
U8
X1
U16
U9
U10
U11
U12
U13
U14
U15
U20
U17
U18
U19
U23
U22
U21
J8
J9
J5 J6
J4
J2
CN1
J7
U29
U28
J12
J11
The MPA-100 occupies an 8 byte block of I/O address space which may be located
anywhere within the available I/O address space in the system.
Communication on the MPA-100 is controlled by a serial communications controller,
hereafter referred to as the SCC (U17). The MPA-100 is compatible with several different types
of SCC, all of which can support asynchronous formats, byte-oriented protocols such as IBM
Bisync, and bit-oriented protocols such as HDLC and SDLC. The SCCs also offer internal
functions such as on-chip baud rate generators, and digital phase-lock loops (DPLL).
The MPA-100 also supports Direct Memory Access (DMA) and interrupts. DMA
channels 1 - 3 can be used for high data transfer rates. Interrupt levels 2-7, 10-12, and 14-15 are
available.
MPA-100 User's Manual 1-1