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Spinpoint M8 Product Manual REV 2.3
5.2.3.5 Analog to Digital Converter (ADC) and FIR ................................................................................ 31
5.3 SERVO SYSTEM
................................................................................................................................32
5.4 R
EAD AND WRITE OPERATIONS
......................................................................................................32
5.4.1 The Read
Channel...........................................................................................................32
5.4.2 The Write
Channel ..........................................................................................................33
5.5 F
IRMWARE FEATURES
.....................................................................................................................33
5.5.1 Read Caching
.................................................................................................................33
5.5.2 Write
Caching
.................................................................................................................34
5.5.3 Defect Management
........................................................................................................35
5.5.4 Automatic Defect Allocation
...........................................................................................35
5.5.5 Multi-burst ECC Correction
...........................................................................................35
5.5.6
SMART............................................................................................................................35
CHAPTER 6 SATA II INTERFACE
.................................................................................................37
6.1 INTRODUCTION
................................................................................................................................37
SATA
Terminology....................................................................................................................................37
6.2 P
HYSICAL INTERFACE
.....................................................................................................................39
6.3 S
IGNAL SUMMARY
...........................................................................................................................39
6.3.1 Signal
Descriptions.........................................................................................................39
6.3.2 I/O Register - Address
....................................................................................................40
6.3.3 Control Block Register Descriptions
..............................................................................40
6.3.3.1 Alternate Status Register (ex. 3F6h) ............................................................................................. 40
6.3.3.2 Device Control Register (ex. 3F6h)............................................................................................... 41
6.3.4 Command Block Register Descriptions
..........................................................................41
6.3.4.1 Data Register (Ex. 1F0h)............................................................................................................... 41
6.3.4.2 Features Register and Feature Extended Register (Ex. 1F1h) ....................................................... 41
6.3.4.3 Sector Number Register and Sector Number Extended Register (Ex. 1F3h) ................................ 41
6.3.4.4 Error Register (Ex. 1F1h) .............................................................................................................. 41
6.3.4.5 Sector Count Register and Se
ctor Count Extended Register (Ex. 1F2h) ....................................... 42
6.3.4.6 Cylinder High Register and Cylinder High Extended Register (Ex. 1F5h) ................................... 42
6.3.4.7 Cylinder Low Register and Cylinder Low Extended Register (Ex. 1F4h) .................................... 42
6.3.4.8 Command Register (Ex. 1F7h)...................................................................................................... 42
6.3.4.9 Device Register (Ex. 1F6h) .................................................................................................
.......... 42
6.3.4.10 Status Register (Ex. 1F7h) ............................................................................................................ 43
CHAPTER 7 SATA II FEATURE
SET .............................................................................................44
7.1 DEVICE ACTIVITY SIGNAL
..............................................................................................................44
7.2 S
TAGGERED SPIN-UP DISABLE CONTROL
.......................................................................................44
7.3 A
UTO-ACTIVATE IN DMA SETUP FIS
............................................................................................44
7.4 N
ATIVE COMMAND QUEUING (NCQ)
.............................................................................................44
7.5 P
HY. EVENT COUNTERS
..................................................................................................................45
7.6 S
OFTWARE SETTINGS
P
RESERVATION
............................................................................................46
7.7 SATA P
OWER
M
ANAGEMENT
.........................................................................................................46
CHAPTER 8 ATA COMMAND DESCRIPTIONS
..........................................................................47
8.1 COMMAND
T
ABLE
............................................................................................................................47
8.2 C
OMMAND
D
ESCRIPTIONS
...............................................................................................................48
8.2.1 Check Power Mode
(E5h)...............................................................................................48
8.2.2 Download Micro Code
(92h)
..........................................................................................49
8.2.3 Device Configuration Overlay
(B1h)
..............................................................................49
8.2.4 Execute Device Diagnostics
(90h) ..................................................................................51
8.2.5 Flush Cache (E7h, EAh:
extended).................................................................................51
8.2.6 Format Track (50h)
........................................................................................................51
8.2.7 Identify Device (ECh)
.....................................................................................................51
8.2.8 Idle
(E3h)
........................................................................................................................57
8.2.9 Idle Immediate (E1h)
......................................................................................................57
8.2.10 Initialize Device Parameters
(91h)
.................................................................................58
8.2.11 NOP
(00h).......................................................................................................................58
8.2.12 R
ead Buffer
(E4h) ...........................................................................................................58
8.2.13 Read DMA (C8h,
25h:extended).....................................................................................58