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M8 Product Manual REV
2.3
42
DEV is reserved.
Bit0-bit3 is defined for the binary coded address of the head to be selected in CHS mode (e.g. if H3
through HS0 are 0011b, respectively, then head 3 will be selected). HS3 is the most significant bit. In 28
bit LBA mode bit0-3 HS3 contains bits 24-27 of the LBA. After command completion, this register is
updated to reflect the currently selected disk address.
LBA is to select the Logical Block Addressing Mode. When LBA=0, disk addressing is by CHS mode.
When LBA=1, disk addressing is b
y LBA mode. This bit was set to zero when the ATA drive didn’t
support LBA mode.
6.3.4.10 Status Register (Ex. 1F7h)
This register contains the drive status. The contents of this register are updated at the completion of each
command. When BSY is cleared, the other bits in this register become valid within 400 nsec. If BSY=1, no
other bits in this register are valid. If the host reads this register when an interrupt is pending, it is considered
to be the interrupt acknowledge. Any pending interrupt is clear
ed whenever this register is read.
7
6
5
4
3
2
1
0
BSY
DRDY
#
#
DRQ
Obsolete
Obsolete
ERR
BSY (Busy) is set whenever the drive has access to the Command Block registers. The host should not
access the Command Block registers when BSY=1. When BSY=1, a read of any Command Block register
returns the contents of the Status register.
DRDY (Drive Ready) indicates that the drive is capable of responding to a command. When there is an
error, this bit does not change until the host reads the Status register. Then the bit again indicates the current
readiness of the
drive. This bit clears at power-on and remains clear until the drive is ready to accept the
command.
DRQ (Data Request) indicates that the drive is ready to transfer a word or byte of data between the host and
the drive.
ERR (Error) indicates that an error occurred during execution of the previous command. The bits in the
Error register have additional information regarding the cause of the error.