Filter
Top Products
ATAPI Interface Chapter 5
STT8000A Product Manual Page 37
Word Description Value Meaning
53 Field Validity 0002h Fields 54-58 not valid.
Fields 64-70 valid
54-56 Current Cylinder/Heads/Sectors 0000h Unsupported
57-58 Current Capacity 0000h Unsupported
59 Reserved 0000h —
60-61 User Addressable Sectors 0000h Unsupported
62 Single Word DMA Mode 0407h Selected DMA mode 2 (Upper Byte),
DMA modes 2,1,0 Supported.
63 Multi Word DMA Mode 0407h Selected DMA mode 2 (Upper Byte)
DMA modes 2, 1, 0 supported.
64 Enhanced PIO Mode 0003h PIO Mode 3 and 4 Supported
65 Minimum Multi Word DMA Cycle Time 0078h Mode 2 (120 nanoseconds)
66 Recommended Multi Word DMA Cycle
Time
0078h Mode 2 (120 nanoseconds)
67 Minimum PIO Cycle Time w/o IORDY 0078h Mode 4 (120 nanoseconds)
68 Minimum PIO Cycle Time with IORDY 0078h Mode 4 (120 nanoseconds)
69-255 Reserved/Vendor Unique 0000h —
ATAPI Packet Command (A0h)
Before issuing the ATAPI Packet command, the host writes to the Byte Count
register (high and low) the maximum/preferred number of bytes to be transferred in
a single PIO DRQ. For Data Transfer commands (READ and WRITE), this value is
assumed to be greater than or equal to 512 and is ignored.
ATAPI Soft Reset (08h)
The ATAPI Soft Reset command performs a complete microprocessor reset.
Current physical and logical position is lost, and if a tape is present, a LOAD
sequence is performed, resulting in a Ready at BOP0 condition (with Unit Attn).
The DSC is set to 1 before the BSY bit is cleared.