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ATA COMMAND BLOCK AND SET DESCRIPTION SSD-HXXX(I)-3650 DATA SHEET
SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
DOCUMENT: 3650H-02DSR JUNE 17, 2008 PAGE 35
Idle — 97h, E3h
When issued by the host, the device’s internal controller sets the BSY bit,
enters the Idle mode, clears the BSY bit, and generates an interrupt. If the
sector count is non-zero, it is interpreted as a timer count with each count
being 5ms, and the automatic power-down mode is enabled. If the sector
count is zero, the automatic power-down mode is disabled.
Table 36: Idle — 97h, E3h
Register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Feature X
Sector Count Timer Count (5ms increments)
Sector Number X
Cylinder Low X
Cylinder High X
Drive Head X X X Drive X
Command 97h or E3h