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Spectrum Signal Processing Monaco Technical Reference
Processor Nodes
Part Number 500-00191
15
Revision 2.00
2.2. Synchronous Burst SRAM
The board provides 128K of 32-bit synchronous burst SRAM (SBSRAM) on each ‘C6x
local bus. The Monaco board supports 1 wait state operation.
2.3. Synchronous DRAM
The board provides 4M of 32-bit synchronous DRAM on each ‘C6x bus. The Monaco
board supports 1 wait state operation. An additional 4M of 32-bit synchronous DRAM
per DSP can also be supported on a PEM module.
Burst data transfer rates from CPU to SDRAM are 400 Mbytes/s on a Monaco with
200 MHz TMS320C6201 chips.
2.4. Processor Expansion Module
The Processor Expansion Module (PEM) provides a simple and flexible interface from
the DSP to I/O. It is similar to a PMC module, although physically narrower.
The Monaco board is designed to support two DSPs per PEM site, with a pair of
connectors for each DSP. While both DSP devices share the same PEM, the two DSP
buses are kept separate to allow very fast PEM data transfer rates.
The PEM is capable of booting the DSPs from local ROM, with up to 4 MBytes of
addressable boot space available to each DSP.
Refer to the PEM Specification for mechanical and functional details of the PEM
interface.
2.5. Host Port
A separate A24 VMEbus Slave interface is used for direct access to the DSP’s Host Port
Interface. This interface can be used for downloading code and as a control path from the
host to the DSP. Data transfer rates depend upon both the code executing in the DSP and
the VMEbus Master performing the transfers, but can be as high as 30 Mbytes/second.
Jumper block JP1 selects the VME A24 base address for this slave interface.
2.6. Interrupt Lines
There are four external interrupt inputs on each ‘C6x. They are INT4, INT5, INT6, and
INT7. All four must be configured as rising-edge triggered interrupts upon initialization.
See the Interrupt Handling chapter for further information.