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Monaco Technical Reference Spectrum Signal Processing
Interrupt Handling
40
Part Number 500-00191
Revision 2.00
8.2. DSP~LINK3 Interrupts to Node A
The four active-low interrupts from the DSP~LINK3 interface are logically OR’ed and
routed to the INT7 interrupt input of the node A ‘C6x. The open-collector signals are de-
bounced. The interrupts are not latched on the Monaco board and must be cleared on the
DSP~LINK3 board that generated them.
PEM INT1
PEM INT2
PEM INT1
PEM INT2
PEM INT1
PEM INT2
PEM INT1
PEM INT2
INT 7
INT 6
INT 5
INT 4
Node A
'C6x
INT 7
INT 6
INT 5
INT 4
INT 7
INT 6
INT 5
INT 4
INT 7
INT 6
INT 5
INT 4
INT0
INT1
INT2
INT3
DSP~LINK3
Interface
Interrupts
Node B
'C6x
Node C
'C6x
Node D
'C6x
PCI Interrupt
PCI Interrupt
PCI Interrupt
PCI Interrupt
PCI Bus
Interrupts
INTA
INTB
INTC
INTD
Hurricane
SCV64 Interrupt
BUSERR_D
VINTD
BUSERR_C
VINTC
BUSERR_B
VINTB
BUSERR_A
VINTA
KIPL D Enable
KIPL C Enable
KIPL B Enable
KIPL A Enable
Note
‘C6x interrupts
are rising edge-
triggered.
VME Interrupt
VME Interrupt
VME Interrupt
VME Interrupt
De-Bounce Logic
Hurricane
Hurricane
Hurricane
De-Bounce Logic
Hurricane
Figure 12 Interrupt Routing