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CXP854P60
∗1
VIN and VOUT should not exceed VDD + 0.3V.
∗2
The large current driver for the PD and PF ports is a N-ch transistor.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Supply voltage
Input voltage
Output voltage
Medium voltage tolerance output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
Vpp
VIN
VOUT
VOUTP
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
–0.3 to +7.0
–0.3 to +13.0
–0.3 to +7.0
∗1
–0.3 to +7.0
∗1
–0.3 to +15.0
–5
–50
15
20
130
–10 to +75
–55 to +150
1000
600
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
mW
Incorporated PROM
Pins PF0 to PF3
Total of all output pins
Excludes large current output
Large current output
∗2
Total of all output pins
SDIP
QFP
Item Symbol Ratings Unit Remarks
Absolute Maximum Ratings (Vss = 0V)
Supply voltage
High level
input voltage
Low level
input voltage
Operating temperature
5.5
5.5
5.5
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
V
V
V
V
V
V
V
V
V
V
°C
Item Symbol Min. Max. Unit Remarks
4.5
3.5
2.5
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–10
Vpp
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
Safe operating range
Safe operating range for low speed data
∗
1
Safe operating range for data retention during STOP
∗5
I
2
C Schmitt input included
∗2
CMOS Schmitt input
∗3
EXTAL pin
∗4
I
2
C Schmitt input included
∗2
CMOS Schmitt input
∗3
EXTAL pin
∗4
VDD
∗
1
Rating for 1/16 frequency mode and sleep mode.
∗
2
Normal input port (All pins PA, PB, PC, PE2 to PE5), PF4 to PF7 pins.
∗
3
Includes PD0/INT2, PD1/SCK, PD2, PD3/SI, PD4/HS0, PD5/HS1, PD6/RMC, PD7/EC, PE0/INT0, PE1/INT1,
HSYNC, VSYNC, RST pins.
∗
4
Rating applies to external clock input only.
∗
5
Vpp and VDD should be set to a same voltage.
Recommended Operating Conditions (Vss =0V)
Vpp = VDD