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3.3.1 Advanced Chipset Control
This section allows you to fine tune the chipset configuration.
PhoenixBIOS Setup Utility
Main Advanced Security Power Boot Exit
Advanced Chipset Control
Item Specific Help
X ICH USB Control Sub-Menu
X LAN Control Sub-Menu
Crystal Beach Configure Enable
SERR signal condition
4GB PCI Hole Granularity
Memory Branch Mode
Branch 0 Rank Sparing
Branch 1 Rank Sparing
Enhanced x8 Detection
WatchDog Timer
Enable Multimedia Timer
Parallel ATA:
Serial ATA:
Native Mode Operation:
SATA Controller Mode Option
[Enabled]
[Single bit]
[256 MB ]
[Interleave]
[Disabled]
[Disabled]
[Enabled]
[Disabled]
[No]
[Enabled]
[Enabled]
[Auto]
[Compatible]
F1 Help ↑↓ Select Item -/+ Change Values F9 Setup Defaults
Esc Exit ← → Select Menu Enter Select
X Sub-Menu F10 Previous Values
Crystal Beach Configure Enable
Enable the configuration of memory mapped accesses to the Crystal Beach
Configuration space located in Device 8, Fn 0 and Fn 1.
Enabled / Disabled
SERR signal condition
Select ECC error conditions that SERR# be asserted.
None / Single bit / Multiple bit/ Both
4GB PCI Hole Granularity
This feature is used to select the granularity of PCI hole for PCI resource. If
MTRRs are not enough, we may use this option to reduce the MTRR
occupation.
256MB / 512MB / 1.0GB / 2.0GB