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SPEC NO.
MT220WW 01 V.0
PAGE
9/23
ALL RIGHTS RESERVED ANY PORTION OF THIS DOCUMENT SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED
TO ANY OTHER FORMS WITHOUT
PRIOR
WRITTEN
PERMISSION FROM INNOLUX DISPLAY CORPORATION.
Note 4 : test condition :
(1) V
DD
= 5 V, V
DD
rising time = 470 Ӵs ± 10%
(2) Pattern: Mosaic pattern
(3) Test circuit
Note 5 : LVDS signal definition
VIN
+
= Positive differential DATA & CLK Input
VIN- = Negative differential DATA & CLK Input
VID = VIN
+
– VIN- ,
∆VCM =ΨVCM
+
–VCM-Ψ,
∆VID =ΨVID
+
–VID-Ψ,
VID+ =ΨVIH
+
–VIH-Ψ,
VID- =ΨVIL
+
–VIL-Ψ,
VCM = (VIN
+
+VIN-)/2,
VCM+ = (VIH
+
+VIH-)/2,
VCM- = (VIL
+
+VIL-)/2,
90
%
Ton=470 Ӵs ̈́ 10%
V
DD
M2
M1
1K
C3
47K
R1
C1
5 V
12V
VDD ( LCD INPUT)
CONTROL SIGNAL
(HIGH to LOW)
2SK1399
2SK1059
R2
C2
10000pF
1uF
R3
47K
FUSE
1uF