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SPEC NO.
MT220WW 01 V.0
PAGE
12/23
ALL RIGHTS RESERVED ANY PORTION OF THIS DOCUMENT SHALL NOT BE REPRODUCED, COPIED, OR TRANSFORMED
TO ANY OTHER FORMS WITHOUT
PRIOR
WRITTEN
PERMISSION FROM INNOLUX DISPLAY CORPORATION.
c. Input signal timing
Support Input Timing Table
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Description Min. Typ. Max. Unit
period 12.2 16.8 17.9 nS Clock
Dclk
frequency 56 59.6 82 MHz
T
V_TOTAL
V total line number 1059 1080 1100 T
H
T
V_DATA
Data duration 1050 1050 1050 T
H
T
VB
V-blank 9 30 50 T
H
Vertical
f
V
frequency 56 60 76 Hz
T
H_TOTAL
H total pixel number 890 920 1004 DClk
T
H_DATA
Data duration 840 840 840 DClk
Horizontal
T
HB
H-blank 73 80 164 DClk
Note:
Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
Tv
Tvd Tvb
Th
Tc
Thb Thd
DE
DCLK
DE
DATA