Schematic Diagrams
DDR3 Channel B SO-DIMM_1 B - 9
B.Schematic Diagrams
DDR3 Channel B SO-DIMM_1
VDDSPDB
1.5V
1.5V
0.75 V
1.5V
3VS
0.75V
VDDSPD B3V S
M_DATA_B[63:0] 2
M_CAS_B _N 3
M_SCS_ B_N0 3
CK _M _CH1_0 _DN 3
M_RAS_B _N 3
M_ DQS_ B_DP[7: 0] 2
M_MA A_B[ 15: 0] 3
SCLK 7,9,12, 16,18 ,1 9, 3 2
M_WE_B _N 3
M_SCS_ B_N1 3
CK _M _CH1_0 _DP 3
M_SCKE _B [ 1 :0] 3
SDATA 7,9,12,16,18,19,32
CK _M _CH1_1 _DN 3
CK _M _CH1_1 _DP 3
PM_EXTTS_DDR# 7,9
M_SBS_B[2:0] 3
DDR 1_DRAMR ST 3
M_ DQS_ B_DN [7 :0] 2
M_OD T_B [ 1:0 ] 3
1.5V4, 5, 7, 9 ,40,4 3
3VS7,9,1 2,13,15 ..30, 32,39 , 4 1,43
0.75 V7,9,4 0
M_MA A _ B 3
M_MA A _ B 12
M_D ATA_B57
M _DA T A_B [63: 0]
CK_M_ C H1 _0_DP
M_CAS_B_N
M_D ATA_B25
M_SCS_B_N0
PM_EXTTS_DDR#
M_DATA_B 15
M_D ATA_B36
PM_EXTTS_DDR#
DD R1_ DRAM RST
CK_M_ C H1 _0_DN
M_D ATA_B47
M_DQS_B _D N1
M_MA A _ B 4
M_RAS_B_N
M_MA A _ B 13
M_DQS_B_DP[7:0]
SCLK
M_WE_B_N
M_SCS_B_N1
M_D ATA_B58
M_MAA_B[15:0]
M_S B S_B 0
M_SCKE_B[1:0]
M_SCS_B_N0
M_SCS_B_N1
M_D ATA_B26
M_DATA_B 16
M_SCKE_B0
Z0803
M_D ATA_B37
M_SCKE_B1
Z0802
CK_M_ C H1 _1_DP
CK_M_ C H1 _1_DN
Z0801
M_CAS_B _N
M_RAS_B _N
M_WE_ B _N
SA0_DIM1
SA1_DIM1
M_SBS_B[2:0]
SCLK
SDATA
M_ODT_ B 0
M_ODT_ B 1
M_DATA_B 0
SDATA
D DR1_D RAMR ST
M_DQS_B_DP0 M_DATA_B48
M_DQS_B_DN[7:0]
CK_ M_C H1_0_DP
CK_ M_C H1_0_DN
CK_ M_C H1_1_DP
CK_ M_C H1_1_DN
M_DQS_B _D N0
M_MA A _ B 0
M_DQS_B _D N2
M_ODT_B[1:0]
M_MA A _ B 5
DIMM_CA_VREF_B
M_MA A _ B 14
M_D ATA_B59
M_D ATA_B27
M_DQS_B _D P 1
M_DATA_B 17
M_D ATA_B38
M_DATA_B 7
M_D ATA_B49
M_DQS_B _D N3
M_MA A _ B 6
M_D ATA_B28
M_DATA_B 18
M_DQS_B _D P 2
M_D ATA_B39
M_DATA_B 8
M_D ATA_B50
M_DQS_B _D N4
M_MA A _ B 7
M_D ATA_B29
M_DATA_B 19
M_DQS_B _D P 3
M_D ATA_B40
M_DATA_B 9
M_D ATA_B51
M_DQS_B _D N5
M_MA A _ B 8
M_DATA_B 1
M_DATA_B 20
M_D ATA_B30
M_D ATA_B60
M_DQS_B _D P 4
M_DATA_B 10
M_D ATA_B41
M_D ATA_B52
M_DQS_B _D N6
M_MA A _ B 9
M_DATA_B 2
M_DATA_B 21
M_D ATA_B31
M_DATA_B 11
M_D ATA_B61
M_D ATA_B42
M_DQS_B_DP5 M_DATA_B53
M_DQS_B _D N7
M_DATA_B 3
M_D ATA_B22
M_D ATA_B32
M_DATA_B 12
M_D ATA_B62
M_D ATA_B43
M_DQS_B _D P 6
M_S B S_B 1
M_D ATA_B54
M_DATA_B 4
M_D ATA_B33
M_D ATA_B44
M_D ATA_B63
M_DQS_B _D P 7
M_MA A _ B 1
M_MA A _ B 10
M_S B S_B 2
M_D ATA_B55
M_DATA_B 5
M_D ATA_B23
M_D ATA_B34
M_DATA_B 13
M_D ATA_B45
M_MA A _ B 2
M_MA A _ B 11
M_D ATA_B56
M_DATA_B 6
M_D ATA_B24
M_D ATA_B35
M_DATA_B 14
M_D ATA_B46
M_MA A_B1 5
DIMM_CA_VREF_B
Z0805
Z0809
Z0810
Z0804
Z0806
Z0811
Z0808
Z0807
JDI MM2B
DDR3_SODIMM1_204P
75
76
81
82
87
88
93
94
99
10 0
10 5
10 6
19 9
77
12 2
12 5
1
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
GND2
GND1
204
203
12 6
30
19 8
11 1
11 2
11 8
11 7
12 3
12 4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
NC 1
NC 2
NC TEST
VREF_DQ
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
G2
G1
V TT2
V TT1
VREF_CA
RESET#
EVENT#
VDD13
VDD14
VDD16
VDD15
VDD17
VDD18
NC 1
NC _0 4
R274 0_04
R266 0_04
C113
4.7U_6.3V_06
C141
.1 U_10V_X7R _04
R267 0_04
C117
1 0U_ 10V_ 08
R275 0_04
+
C1 49
1 00U_6 .3V _ B
R272 0_04
R265 0_04
JD IMM2A
DDR3_SODIMM1 _2 04P
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
109
108
110
113
115
114
121
73
74
101
103
102
104
200
202
201
197
11
28
46
63
136
153
170
187
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
116
120
79
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
BA0
BA1
RAS#
WE#
CAS#
S0#
S1#
CKE0
CKE1
CK0
CK0#
CK1
CK1#
SDA
SCL
SA1
SA0
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
ODT0
ODT1
BA2
R273 0_04
R264 0_04
R276
10 K _04
C1 38
4.7U_6.3V_ 0 6
C1 18
10 U_ 10V _ 08
C115
.1U _10V_X7 R_04
C114
.1U_10V_X7R_04
R277
10 K _04
R2 71
1K_1%_04
R2 70
1K_1%_04
C1 37
.1U_10V_X7R _04
C14 2
10 U_1 0V _0 8
C469
.1U _10V_X7R_ 04
C120
10U_10V_08
C4 74
.1U_10V_X7R_04
C473
2.2U_16V_X5R_06
C140
*1 0u_10 V _0 8
C1 19
.01U_16V_X7R_04
C136
10 U_1 0V _ 08
C116
1 U_6 . 3 V_04
C1 45
.1U_10V_X7R _04
C139
.1 U_10V_ X7R _0 4
SO-DIMM_1 is placed farther from
the CPU than SO-DIMM_0
Layout note:
ChannelB
MS:8.5 / 5 / 8.5
SL: 4 / 4 / 4
15mils trace
34mils spacing
Layout Note:
CLK0/space/CLK_1
SO-DIMM1
20mils trace
ChannelB
CLOSE TO SO-DIMM_1
SA0
SA1
DIM0 CHA
CHB CHC
Low
Low
Low
LowHigh
High
M_DQS_A_DP8
M_DQS_A_DN8
X58 ? ? ??
???ECC??,
? ? DM ?? ? ? ? OK
M_CB_ECC_B[7:0]
From power 0.75V
Sheet 8 of 47
DDR3 Channel B
SO-DIMM_1