Cypress CYV15G0404DXB Clock User Manual


 
CYV15G0404DXB
Document #: 38-02097 Rev. *B Page 5 of 44
WREN
ADDR[3:0]
DATA[7:0]
Device Configuration and Control Block
= Internal Signal
RXRATE[A..D]
FRAMCHAR[A..D]
RFEN[A..D]
RXCKSEL[A..D]
RFMODE[A..D][1:0]
RXBIST[A..D]
DECMODE[A..D]
DECBYP[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
TXRATE[A..D]
TXCKSEL[A..D]
TXBIST[A..D]
OE[A..D][2..1]
PABRST[A..D]
ENCBYP[A..D]
GLEN[11..0]
FLEN[2..0]
Device Configura-
tion and Control
Interface
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