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Prometheus CPU User Manual V1.44 Page 38
Base + 4 Read/Write Interrupt / DMA / Counter Control
Bit No. 7 6 5 4 3 2 1 0
Name CKSEL1 CKFRQ1 CKFRQ0 ADCLK DMAEN TINTE DINTE AINTE
CKSEL1 Clock source selection for counter/timer 1:
0 = internal oscillator, frequency selected by CLKFRQ1
1 = external clock input CLK1 (DIO C pins must be set for ctr/timer signals)
CKFRQ1 Input frequency selection for counter/timer 1 when CKSEL1 = 1:
0 = 10MHz, 1 = 100KHz
CKFRQ0 Input frequency selection for counter/timer 0.
0 = 10MHz, 1 = 1MHz
ADCLK A/D trigger select when AINTE = 1:
0 = internal clock output from counter/timer 0
1 = external clock input EXTTRIG
DMAEN Enable DMA operation. 1 = enable, 0 = disable.
TINTE Enable timer interrupts. 1 = enable, 0 = disable.
DINTE Enable digital I/O interrupts. 1 = enable, 0 = disable.
AINTE Enable analog input interrupts. 1 = enable, 0 = disable.
NOTE: When AINTE = 1, the A/D cannot be triggered by writing to Base + 0.
Analog output interrupts are not supported on this board.
Multiple interrupt operations may be performed simultaneously. All interrupts will be on the same
interrupt level. The user’s interrupt routine must monitor the status bits to know which circuit has
requested service. After processing the data but before exiting, the interrupt routine must then
clear the appropriate interrupt request bit using the register at Base + 0.
Base + 5 Read/Write FIFO Threshold
Bit No. 7 6 5 4 3 2 1 0
Name X X FT5 FT4 FT3 FT2 FT1 FT0
FT5–0 FIFO threshold. When the number of A/D samples in the FIFO reaches this number,
the board will generate an interrupt and set AINT high (Base + 7 bit 4). The interrupt
routine is responsible for reading the correct number of samples out of the FIFO.
The valid range is 1-48. If the value written is greater than 48, then 48 will be used. If
the value written is 0, then 1 will be used. The interrupt rate is equal to the total
sample rate divided by the FIFO threshold. Generally, for higher sampling rates a
higher threshold should be used to reduce the interrupt rate. However remember that
the higher the FIFO threshold, the smaller the amount of FIFO space remaining to
store data while waiting for the interrupt routine to respond. If you get a FIFO
overflow condition, you must lower the FIFO threshold and/or lower the A/D sampling
rate.