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NV3128 RS-422A Machine-Control Data Routing Switch 4-9
ASYNCHRONOUS TIMING
Asynchronous system timing consists of two signals. The first, derived from
the reference video inputs re-trace interval, activates the pre-loaded
information in the crosspoints double-buffered registers. This action executes
a take. The second timing signal is a system master clock.
A sync stripper derives the vertical retrace pulse and passes it on to a
microprocessor for processing into strobe and write-enable signals.
An oscillator provides the master clock for the entire system. When used on
the NV3128, this oscillator free runs.
PARTITIONING
On the Command Interpreter two banks of DIP switches and their associated
circuitry configure the NV3128 into partitions. Additionally, software versions
supporting various controllers may make use of these switches for
supplementary configuration control.
On the newer Universal Control module, partitioning is set up using UniDiag
and stored in memory.
PARALLEL INTERFACE (COMMAND INTERPRETER ONLY)
Line driver/receivers interface with the parallel RS-422A circuits that
characterize the PESA protocol interface. A programmable gate array and
matrix SRAM work in conjunction to gather and process this very high speed
data.
POWER REGULATION
Power regulator circuitry regulates the incoming raw DC voltage from the
PS2001 power supply to +/-15VDC and +/-5VDC respectively.