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SED1520 Series
EPSON 2–21
SED1520
Series
DC Characteristics (Cont’d)
Ta = –20 to 75 deg. C, V
DD = 0 V unless stated otherwise
Rating
Parameter Symbol Condition Unit Applicable Pin
Min. Typ. Max.
V
OLT IOL = 3.0 mA — — VSS+0.4
OSC2
V
OLC1 IOL = 2.0 mA — — VSS+0.4 V
See note 4 & 5.
V
OLC2 IOL = 120 µA — — 0.8×VSS
Low-level output voltage
V
OLT VSS = –3 V IOL = 2 mA 0.8×VSS
See note 4 & 5.
V
OLC1 VSS = –3 V IOL = 2 mA 0.8×VSS V
OSC2
V
OLC2 VSS = –3 V IOL = 50 µA 0.8×VSS
Input leakage current ILI –1.0 — 1.0 µA See note 6.
Output leakage current I
LO –3.0 — 3.0 µA See note 7.
V5 = –5.0 V — 5.0 7.5 SEG0 to 79,
LCD driver ON resistance R
ON Ta = 25 deg. C kΩ COM0 to 15,
V
5 = –3.5 V — 10.0 50.0 See note 11
Static current dissipation IDDQ
CS
= CL = VDD — 0.05 1.0 µAVDD
fCL = 2 kHz — 2.0 5.0 VDD
During display
R
f = 1 MΩ — 9.5 15.0 µA See note 12,
V
5 = –5.0 V
f
CL = 18 kHz — 5.0 10.0 13 & 14.
I
DD (1)
During display f
CL = 2 kHz 1.5 4.5
V
DD
Dynamic current dissipation V5 = –5 V µA
See note 12 & 13.
V
SS = –3 V Rf = 1 MΩ 6.0 12.0
During access tcyc = 200 kHz — 300 500
I
DD (2) VSS = –3V, µA See note 8.
150 300
During access t
cyc = 200 kHz
Input pin capacitance C
IN Ta = 25 deg. C, f = 1 MHz — 5.0 8.0 pF All input pins
R
f = 1.0 MΩ ±2%,
15 18 21
V
SS = –5.0 V
Oscillation frequency f
OSC kHz See note 9.
R
f = 1.0 MΩ ±2%,
11 16 21
V
SS = –3.0 V
RES
Reset time tR 1.0 — µS
See note 15.
Notes: 1. Operation over the specified voltage range is guaranteed, except where the supply voltage changes
suddenly during CPU access.
2. A0, D0 to D7, E (or RD), R/W (or WR) and CS
3. CL, FR, M/S and RES
4. D0 to D7
5. FR
6. A0, E (or RD), R/W (or WR), CS, CL, M/S and RES
7. When D0 to D7 and FR are high impedance.
8. During continual write acess at a frequency of t
cyc. Current consumption during access is effectively
proportional to the access frequency.
9. See figure below for details
10. See figure below for details
11. For a voltage differential of 0.1 V between input (V
1, …, V4) and output (COM, SEG) pins. All voltages
within specified operating voltage range.
12. SED1520
*
A
*
and SED1521
*
A
*
and SED1522
*
A
*
only. Does not include transient currents due to
stray and panel capacitances.
13. SED1520
*
0
*
and SED1522
*
0
*
only. Does not include transient currents due to stray and panel
capacitances.
14. SED1521
*
0
*
only. Does not include transient currents due to stray and panel capacitances.
15. t
R (Reset time) represents the time from the RES signal edge to the completion of reset of the internal
circuit. Therefore, the SED1520 series enters the normal operation status after this tR.