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SCSI BUS
7-22 C156-E228-02EN
7.6.3 SELECTION phase
An INIT can select a TARG in the SELECTION phase.
Note: I/O signal is false during a SELECTION phase. (The I/O signal
identifies the phase as SELECTION or RESELECTION).
(1) Start sequence without ARBITRATION phase
In systems with the ARBITRATION phase not implemented, the INIT starts the
SELECTION phase in the following sequence (See Figure 7.11).
1) The INIT shall wait for at least Bus Clear Delay after BUS FREE phase
detection.
2) The INIT then asserts its SCSI ID and that of the desired TARG on the data
bus.
3) After waiting at least Deskew Delay × 2, the INIT asserts the SEL signal and
waits for a response from the TARG (BSY signal).
(2) Start sequence with ARBITRATION phase
In systems with ARBITRATION phase implemented, the INIT starts the
SELECTION phase in the following sequence (See Figure 7.11).
1) The INIT shall wait for at least Bus Clear Delay + Bus Settle Delay after
turning SEL signal on during the ARBITRATION phase.
2) The INIT then asserts its SCSI ID and that of the desired TARG on the data
bus.
At this time, the SCSI device becomes an INIT without driving the I/O signal.
3) The INIT releases the BSY signal after waiting at least Deskew Delay × 2.
The INIT shall then wait at least Bus Settle Delay before looking for the
response from the TARG (BSY signal).
(3) Response sequence
When the SCSI device (TARG) detects that the SEL signal and the data bus bit
(DBn) corresponding to its SCSI ID are true and the BSY and I/O signals are false
for more than Bus Settle Delay, it must recognize that itself is selected by the
SELECTION phase. At this time, the selected TARG may sample all bits on the
data bus to identify the INIT's SCSI ID.
The TARG must respond to the INIT by making the BSY signal true within
Selection Abort Time after detecting that itself is selected. If the SCSI ID with
three or more bits is detected on the data bus or a parity error is detected in the
system making the data bus parity bit effective, the TARG must respond to the
SELECTION phase.
The values on the DATA BUS can be changed after this time.