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2 System Board - (SiS Chipset) (Part Number: D4051-63001)
SiS Chipset
Data Path (SiS 5512 Chip)
The SiS 5512 PCI Local Data buffer (PLDB) provides bidirectional data
buffering among the 64-bit Host Data Bus, the 64/32-bit Memory Data Bus,
and the 32-bit PCI Address/Data Bus.
The PLDB incorporates three FIFOs (First In First Out) and one read buffer
among the bridges of the CPU, PCI, and memory buses. This buffering
scheme, among many things, smooths the differences in bandwidths
between the three buses, therefore improving the overall system
performance. During bus operations between the Host, PCI and Memory, the
the PLDB receives control signals from the SiS 5511 PCMC, performs
functions such as latching data, forwarding data to destination bus, data
assemble and disassemble.
The PLDB mainly contains storage elements. The behavior of the Data Path
chip is always controlled by the SiS 5511 Host/PCI bridge.
The main features of the SiS 5512 chip are:
• Supports full 64-bit Pentium Processor data bus.
• Provides a 32-bit interface to the PCI.
• Always sustains 0 Wait Performance on CPU-to-Memory.
• Always streams 0 Wait Performance on PCI-to/from-Memory Access.
• Supports built-in 32-bit General Purpose Register.
• Provides parity generation for memory writes.
• Provides optional parity checker for memory reads.
PCI/ISA Bridge (SiS 5513 Chip)
The SiS 5513 chip is a highly integrated PCI/ISA system I/O
1
(PSIO) device
that includes all the necessary system control logic used in the PCI/ISA
specific applications. The PSIO device serves as a bridge between the PCI
bus and the ISA bus, translates ISA master/DMA device cycles onto the PCI
bus, and serves as a built-in PCI master/slave IDE interface.
It incorporates a seven-channel programmable DMA controller, 16-level
programmable interrupt controller, a programmable timer with three
counters with 256 bytes (CMOS SRAM not used), and an onboard Plug and
1. I/O = Input/Out