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4 BIOS Overview
Order in Which the POST Tests are Performed
0Fh Initialize the local bus IDE
10h Initialize Power Management
11h Load alternate registers with initial POST values
12h Restore CPU control word during warm boot
13h Initialize PCI Bus Mastering devices
14h Initialize keyboard controller
17h Initialize cache before memory autosize
18h 8254 timer initialization
1Ah 8237 DMA controller initialization
1Ch Reset Programmable Interrupt Controller
24h Set ES segment register to 4 GB
26h Enable A20 line
28h Autosize DRAM
29h Initialize POST Memory Manager
2Ah Clear 512 KB base RAM
32h Test CPU bus-clock frequency
33h Initialize POST Dispatch Manager
34h Test CMOS RAM
35h Initialize alternate chipset registers
36h Warm start shutdown
37h Reinitialize the chipset (MB only)
38h Shadow system BIOS ROM
39h Reinitialize the cache (MB only)
3Ah Autosize cache
3Ch Configure advanced chipset registers
Checkpoint
Code
POST Routine Description