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6 Tests and Error Messages
Order in Which POST Tests Are Performed
50h Memory below 1 MB has been tested and initialized. Adjusting the displayed memory size
for relocation and shadowing.
51h Memory size display was adjusted for relocation and shadowing. Testing the memory
above 1 MB.
52h Memory above 1 MB has been tested and initialized. Saving the memory size information.
53h Memory size information and CPU registers are saved. Entering real mode.
54h Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line, parity,
and the NMI.
57h The A20 address line, parity, and the NMI disabled. Adjusting the memory size depending
on relocation and shadowing.
58h Memory size was adjusted for relocation and shadowing. Clearing the Hit <DEL>
message.
59h The Hit <DEL> message is cleared. The <WAIT> message is displayed. Starting the
DMA and Interrupt controller test.
60h DMA page register test passed. Performing the DMA controller 1 base register test.
62h DMA controller 1 base register test passed. Performing the DMA controller 2 base register
test.
65h DMA controller 2 base register test passed. Programming DMA controllers 1 and 2.
66h Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt controller.
62h Test extended memory address lines
7Fh Extended NMI source enabling is in progress.
80h Keyboard test has started. Clearing the output buffer and checking for stuck keys. Issuing
the keyboard reset command.
81h Keyboard reset error or stuck key was found. Issuing the keyboard controller interface test
command.
82h Keyboard controller interface test completed. Writing the command byte and initializing
the circular buffer.
83h Command byte was written and global data initialization has completed. Checking for a
locked key.
84h Locked key checking is over. Checking for memory size mismatch with CMOS RAM data.
Checkpoint
Code
POST Routine Description (Continued)
(A Check Point Code is NOT an error code or error number)