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CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
Figure 9-2. Timer Clock Select Register 2 Format
TCL27
7
TCL26
6
TCL25 0
4
0
3210
FF42H
Address
TCL2
Symbol
TCL22 TCL21 TCL20
5
00H
After
Reset
R/W
R/W
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TCL22 TCL21 TCL20
f
XX/2
3
fXX/2
4
fXX/2
5
fXX/2
6
fXX/2
7
fXX/2
8
fXX/2
9
fXX/2
11
MCS=1
f
X/2
3
fX/2
4
f
X/2
5
f
X/2
6
f
X/2
7
f
X/2
8
f
X/2
9
fX/2
11
MCS=0
f
X/2
4
fX/2
5
fX/2
6
f
X/2
7
f
X/2
8
fX/2
9
f
X/2
10
fX/2
12
Watchdog Timer Count Clock Selection
0
1
1
1
1
×
0
0
1
1
×
0
1
0
1
TCL27 TCL26 TCL25
Buzzer output disable
f
XX/2
9
fXX/2
10
fXX/2
11
Setting prohibited
MCS=1
f
X/2
9
(9.8 kHz)
f
X/2
10
(4.9 kHz)
f
X /2
11
(2.4 kHz)
MCS=0
fX /2
10
(4.9 kHz)
f
X/2
11
(2.4 kHz)
f
X/2
12
(1.2 kHz)
Buzzer Output Frequency Selection
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(2.4 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz)
(1.2 kHz)
Cautions 1. When rewriting TCL2 to other data, stop the timer operation beforehand.
2. Set 0 to bits 3 and 4.
Remarks 1. f
XX : Main system clock frequency (fX or fX/2)
2. f
X : Main system clock oscillation frequency
3. × : don’t care
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X = 5.0 MHz