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536EX Chipset Developer’s Manual 103
Intel Confidential
Parallel Host Interface 16C450/16C550A UART
• LSR7 indicates when any errors occur in the RCVR FIFO.
• TEMT indicates when both the XMIT FIFO and Shift registers are empty.
• The THRE bit (LSR5) is set to ‘1’ whenever the XMIT FIFO is empty.
• LSR1 through LSR4 specify when a break interrupt, framing error, parity error, or overrun
error occurs.
• The DR bit (LSR0) is set to ‘1’ as long as there is at least one byte in the RCVR FIFO.
Unlike FIFO interrupt mode, FIFO polled mode does not support buffer trigger levels or time-out
conditions.