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Errata
12 Intel
®
80303 and 80302 I/O Processors Specification Update
Errata
1. Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by
ECC Control Register
Problem: The ECC Control Register ECCR is described as having the ability to select multi-bit error and/or
single-bit error reporting (see Table 13-24 on page 13-31 of the Intel
®
80303 I/O Processor
Developer’s Manual). However, the algorithm does not allow individual enabling; that is, the
reporting is either on or off for both multi-bit and single bit error reporting.
Implication: The error reporting selection (enabled or disabled) will apply to both multi-bit and single-bit errors.
Workaround: There is no current workaround. If either the ECCR.0 bit or the ECCR.1 bit is selected for
reporting, then both multi-bit and single-bit error reporting are enabled. If neither bit is selected for
reporting, then both multi-bit and single-bit error reporting are disabled.
Status: NoFix. See the Table “Summary Table of Changes” on page 7.
2. Instruction Sequence Can Scoreboard a Register Indefinitely
Problem: Register scoreboarding maintains register coherency by preventing parallel execution units from
accessing registers for which there is an outstanding operation (see section 3.2.3 in the Intel
®
80303 I/O Processor Developer’s Manual).
An instruction sequence that coincides with some specific instruction cache conditions can
scoreboard a local or global register indefinitely. When this happens, processing can stall at the
next access to that register, awaiting a scoreboard release that does not come. In that case, external
bus accesses cease.
A hardware reset is the only way to release the scoreboard.
The following three conditions are required to scoreboard a register:
1. Execution of the following three-instruction sequence:
a. emul
b. ld, ldos, ldis, ldob, or ldib
c. mulo or muli
Only two-word, MEMB format load instructions that execute in two clock cycles cause the
failure. Table 1 lists all the versions of these instructions that can produce this failure. Any
version can be used for each instruction and still produce the failure as long as the sequential
order is maintained.
2. The emul must appear at address 0xXXXXXXX8.
3. Instruction caching must be enabled. The emul instruction must be fetched from external
memory along with the first word of the load instruction. Also, the second word of the load
and the multiply instruction must already reside in cache. To accomplish this, the code must
have run once in order to load the instructions into cache followed by code which causes the
invalidation of the cache line containing the emul instruction. At this point, re-execution of the
code sets up the failure condition.
Once the failure condition occurs, the processor will continue code execution until an instruction
using the scoreboarded register is encountered, then indefinite processor stall will occur.