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166 Software Developer’s Manual
Ethernet Interface
Once PHY Auto-Negotiation is complete, the PHY asserts the link indication signal. Software
MUST set the “set link up” bit in the Device Control Register (CTRL.SLU) before the Ethernet
controller recognizes the link. Setting the SLU bit permits the MAC to recognize the LINK signal
from the PHY, which indicates the PHY has gotten the link up, and to receive and transmit data.
8.6.2.2 Link Speed
The speed of the link in GMII/MII mode can be determined by several methods with the Ethernet
controller. These include:
• Software forced configuration of link speed
• Automatically detecting the Auto-Negotiated speed from the PHY
• Direct indication of speed configuration from the PHY
These methods are discussed in the following sections.
8.6.2.2.1 Forcing Speed
There can be circumstances when the software driver must force the link speed of the Ethernet
controller. This can occur when the link is manually configured.
The software driver can force speed in the MAC by setting the CTRL.FRCSPD (force-speed) bit to
1b, and then setting the speed bits in the Device Control register (CTRL.SPEED) to the desired
speed setting. See Section 13.4.1 for details.
When forcing the Ethernet controller to a specific speed configuration, the driver must also ensure
the PHY is configured to a speed setting consistent with the MAC. This statement implies that
software accesses to the PHY either force the speed, or read the MII management status register
bits that indicate link speed within the PHY itself.
Forcing the speed setting with CTRL.SPEED also can be accomplished by setting the
CTRL_EXT.SPD_BYPS bit. This bit bypasses the internal clock switching logic, and gives
complete control to the driver when the speed setting takes place. The CTRL.FRCSPD bit uses the
internal clock switching logic, which delays the effect of the speed change.
8.6.2.2.2 Using Auto-Speed Detection (ASD)
The Ethernet controller provides a method in hardware for automatically sensing the speed of the
link by observing the receive clock signal generated by the PHY once the link is established. The
Auto-Speed Detection (ASD) function is enabled via the ASDE bit in the Device Control register
(CTRL.ASDE). ASD provides a method of determining the link speed without the need for
software accesses to the MII management registers. ASD is not supported in Internal Serdes mode
for the
82546GB/EB and 82545GM/EM or TBI mode for the 82544GC/EI.
In internal PHY mode, the internal receive clock input operates at the byte rate of the link interface.
By sensing this clock, the Ethernet controller makes a determination of the link speed and sets the
proper configuration in the control registers without software intervention.
The ASD function is initiated upon the assertion of a valid link by the PHY via an internal signal
input. After the speed is detected, the Device Control and Device Status register bits are set and
reflect the speed of the link. As described earlier, software must set the CTRL.SLU bit to allow the
speed selection to take effect.