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6 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Adapter and Controller Overview
2.2 Intel Fast Ethernet MAC Features
2.2.1 82557 Features
• Glueless 32-bit, zero wait state PCI bus master interface compliant with PCI Specification,
Revision 2.1.
• 10 and 100 Mbps support in compliance with IEEE 802.3 10BASE-T and 802.3u 100BASE-
TX.
• Fast back-to-back transmit interframe spacing (IFS) of 960 ns in 100 Mbps networks and 9.6
µs in 10 Mbps networks.
• On-chip Control/Status Register (CSR) incorporating the System Control Block (SCB).
• Simple and flexible packet support with Dynamic transmit chaining.
• Packed Transmit Buffer Descriptors (TBDs).
• Early transmit complete indication.
• Simple receive packet support allows early receive interrupt support for concurrent processing
(in simplified mode).
• IEEE Media Independent Interface (MII) compliant PHY interface other MII compliant PHYs.
• Full and half duplex transmit and receive capability.
• Separate on-chip receive and transmit FIFOs.
• On-chip network management counters.
• EEPROM support.
• Optional Flash ROM support (256 Kbytes or 1 Mbyte).
2.2.2 82558 Features
For the most part, the 82558 is a superset of the 82557. In addition to incorporating the features of
the 82557, it also includes the following:
• Backward compatible to 82557 software.
• Integrated 100BASE-TX PHY.
• IEEE 802.3u auto-negotiation support in 10BASE-T, 100BASE-TX, full duplex and full
duplex flow control configurations.
• Auto-polarity correction for 10BASE-T.
• Optimized PCI interface with support for the memory write and invalidate PCI command.
• Automatic read of EEPROM (programmable ID).
• IEEE 802.3x flow control capable.
• PHY based flow control support when the internal 100BASE-TX PHY is used.
• Advanced Configuration and Power Interface (ACPI) Specification and PCI Power
Management Specification compliant.
• Remote power up support (for Magic Packet*).