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10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 133
Physical Layer Interface
7.5.2.1 PHY Stand Alone (PHYSA) Mode
Only the 82558 supports a special mode where its PHY unit can be used with an external controller
through an MII-like interface. This mode is not fully MII compliant and should be used with care.
The PHY Stand Alone (PHYSA) mode is enabled if the PHYSA bit (EEPROM word 0Ah, bit D4)
is set in the EEPROM. If this bit is set, the 82558 regards the FLD3 pin as a PHYSA input pin.
When this pin is asserted (high), the 82558 enters PHYSA mode in which:
• The 82558 MII is enabled in PHY mode (TXD are inputs, RXD are outputs, etc.).
• The 82558 operates through this MII as if it is an 82555 in DTE mode.
• The 82558 CSMA unit is disabled (has no clock).
• The PCI unit is functional but is expected to be non-operational (isolated).
The MII-like interface is intended for use with one on-board controller and may not meet the MII
timing specification. No additional PHY device (or MII connector) should be connected to this MII
bus.
The CLK signal must be provided for at least 6000 clocks after Reset or Alternate Reset is de-
asserted. The Isolate signal is to be de-asserted and the Clock signal active for at least 4 clocks if a
Reset signal or Alternate Reset signal is to be propagated into the 82558.
The 82558 is not automatically reset upon entering PHYSA mode. In PHYSA mode the Alternate
Reset pin affects only the PCI and CSMA units. It does not propagate into the PHY unit. The PCI
and CSMA should be reset by asserting the Alternate Reset pin.
The settings used by the PHY prior to entering PHYSA mode may not be supported by the external
controller (for example, full duplex flow control).
In PHY Stand Alone mode, a typical event sequence is as follows:
• RST# or ALTRST# is asserted.
• ISOLATE# should be asserted after at least 4 CLK clocks.
• The PCI bus may be stopped 4 CLKs after ISOLATE# is asserted (excluding CLK).
• RST# or ALTRST# is de-asserted, but CLK is still running.
• The 82558 reads the EEPROM (6000 CLK clocks).
• The 82558 enters PHYSA enable state.
• PHYSA pin is asserted.
• ALTRST# should be asserted after at least 4 PHY clocks.
To exit the PHY Stand Alone mode, the following sequence of events occurs:
• PHYSA pin is de-asserted.
• The PCI bus is activated and CLK is valid.
• ISOLATE# is de-asserted.
• RST# or ALTRST# or a software reset is recommended.