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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 9
Power Management Interface 3
The 82557 has no power management support. The 82558 added support for the Advanced
Configuration and Power Interface (ACPI) Specification and limited support for Wake on LAN
(WOL). The 82558 B-step upgraded and expanded the WOL capability, while the 82559 expanded
and simplified the WOL functionality even more.
3.1 Low Power Mode Requirements
The 82558, 82559, 82550, and 82551 adhere to the emerging power management standards as
defined in:
• PCI Bus Power Management Interface Specification, Revision 1.0.
• Advanced Configuration and Power Interface Specification (ACPI), Rev 1.0; December 22,
1996.
• Device Class Power Management Reference Specification - Network Device Class, Revision
1.0.
These three specifications define how a PCI network device can be controlled in an OS Directed
Power Management (OSPM) environment. These devices all adhere to these specifications.
Additionally, they support bus isolation within the chip and Wake on LAN (WOL) capabilities.
3.2 Device Power States
Currently, operating systems only support the D0 and D3 power states. However, starting with the
82558, the Intel Fast Ethernet controller family supports all four power states as defined in the PCI
Power Management Specification. These power states are named D0, D1, D2 and D3. D0 is the
maximum powered state, and D3, the minimum powered state.
3.3 Power Management Registers
The 82558, 82559, 82550, and 82551 support power management registers:
• Power Management Capability Pointer (Cap_Ptr)
• Power Management Capabilities (PMC)
• Power Management Control/Status Register (PMCSR)
• Power Management Driver Register (PMDR)
The first three registers are located in PCI configuration space and are defined in the PCI Power
Management Specification. It is part of the device CSR, which is mapped into system memory and
I/O space.