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2. Memory speed differences account for some slight variations in performance difference
between models.
3. CPW values for Power System models introduced in October 2008 were based on IBM i 6.1
plus enhancements in post-release PTFs.
C.1.4 CPW values for IBM Power Systems
- IBM i operating system
9200-326502 - 82x4MB / 32MB4.24966550 (8204-E8A)
7750-276002 - 82x4MB / 32MB3.54965550 (8204-E8A)
1560042x4MB / 0MB4.25635520 (8203-E4A)
830022x4MB / 0MB4.25634520 (8203-E4A)
430012x4MB / 0MB4.25633520 (8203-E4A)
Processor
CPW
CPU
(2)
Range
L2/L3 cache
(1)
per chip
Chip Speed
GHz
Processor
Feature
Model
Table C.1.4. CPW values for Power System Models
*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache
between two processor cores.
2. The range of the number of processor cores per system.
3. Memory speed differences account for some slight variations in performance difference
between models.
4. CPW values for Power System models introduced in October 2008 were based on IBM i 6.1
plus enhancements in post-release PTFs.
C.2 V6R1 Additions (August 2008)
C.2.1 CPW values for the IBM Power 595 - IBM i operating system
2562001280009380066400355002x4MB / 32MB42004694595 (9119-FHA)
29470014790010810077000410002x4MB / 32MB50004695595 (9119-FHA)
64 cores
(2)
(2x32)
32 cores24 cores16 cores8 cores
L2/L3 cache
(1)
per chip
Chip Speed
MHz
Processor
Feature
Model
Processor CPW
Table C.2.1. CPW values for Power System Models
*Note: 1. These models have a dedicated L2 cache per processor core, and share the L3 cache
between two processor cores.
2. This configuration was measured with two 32-core partitions running simultaneously on a 64
core system
C.3 V6R1 Additions (April 2008)
C.3.1 CPW values for IBM Power Systems - IBM i operating system
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008 Appendix C CPW, CIW and MCU for System i Platform 346