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IXP1200 Network Processor Family ATM OC-3/12/Ethernet IP Router Example Design
Application Note 57
Modified on: 3/20/02,
10.0 Document Conventions
In illustrations of 32-bit registers, or data structures in memory; smaller addresses appear toward
the top of the figure, - as they would appear in a memory dump on the screen. Bit positions are
numbered from the right to the left.
Bytes are numbered from left to right as shown in the array in Figure 37, as well as in the example
byte sequence inFigure 38. Bytes of a word are numbered starting at the most significant byte.
11.0 Acronyms & Definitions
Figure 37. Illustration of Array of 32-bit Words
bits
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
address
n
Byte 0 Byte 1 Byte 2 Byte 3
address
n+1
Byte 4 Byte 5 Byte 6 Byte 7
address
n+2
Byte 8 Byte 9 Byte 10 Byte 11
Figure 38. Illustration of Byte Sequence
012345678910111213141516...Bytes
Ethernet Dest. Address Ethernet Source Address Type IP... .. IP
Figure 39. Definitions
Term Definition
AAL ATM Adaptation Layer
AAL5 ATM Adaption Layer 5 (data)
API Application Programming Interface
ARP (or ATM ARP) Address Resolution Protocol
ATM Asynchronous Transfer Mode
BDQ Buffer Descriptor Queue
CRC Cyclic Redundancy Check
CS (or AAL5-CS) Convergence Sub-Layer
DLL Dynamic Link Library
DWBF
Developer’s Workbench - Integrated Development
environment for the IXP1240 Network Processor
Fast Port A port that has its own dedicated status lines
GPR
IP Internet Protocol
MAC Media Access Controller