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292 Rabbit 3000 Microprocessor
B.1.8 Secondary Watchdog Timer
The secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by
the 32.768 kHz clock. The timer is off by default, and is enabled by writing a 0x5F to the
WDTCR. The secondary watchdog timer register (SWDTR) holds the time constant
value. Depending on the value loaded into the SWDTR, the timer can request an interrupt
anywhere from 30.5 µs to 7.8 ms. If a 0x5F is written to the WDTCR prior to end of the
countdown period, the timer will not request an interrupt. If the counter counts down to
zero, a level-3 interrupt is generated. The SWDT is intended as a safety net for the peri-
odic interrupt, and would normally be restarted in the service routine for the periodic inter-
rupt. Although the hardware was intended to primarily be used by an operating system
when the System/User mode is enabled, it can be used as a configurable periodic interrupt
as well.
Table B-16. Watchdog Timer Control Register—Updated
Watchdog Timer Control Register (WDTCR) Address = 0x0008)
Bit(s) Value Description
7:0 0x5A Restart the watchdog timer, with a 2-second time-out period.
0x57 Restart the watchdog timer, with a 1-second time-out period.
0x59 Restart the watchdog timer, with a 500 ms time-out period.
0x53 Restart the watchdog timer, with a 250 ms time-out period.
0x5F Restart the secondary watchdog timer.
other No effect on watchdog timer or secondary watchdog timer.
Table B-17. Secondary Watchdog Timer Register
Secondary Watchdog Timer Register (SWDTR) (Address = 0x000C)
Bit(s) Value Description
7:0
The time constant for the secondary watchdog timer is stored. This time constant
will take effect the next time that the secondary watchdog counter counts down
to zero. The timer counts modulo n + 1, where n is the programmed time
constant. The secondary watchdog can be disabled by writing the sequence
0x5A-0x52-0x44 to this register.