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User’s Manual 313
Table B-27. PWM LSB 2 and 3 Registers
PWM LSB x Register (PWL2R) (Address = 0x008C)
(PWL3R) (Address = 0x008E)
Bit(s) Value Description
7:6 write The least significant two bits for the Pulse Width Modulator count are stored.
5:4 00 Normal PWM operation.
01 Suppress PWM output seven out of eight iterations of PWM counter.
10 Suppress PWM output three out of four iterations of PWM counter.
11 Suppress PWM output one out of two iterations of PWM counter.
3:1 These bits are ignored and should be written with zero.
0
0 PWM output High for single block.
1 Spread PWM output throughout the cycle.