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SP Switch Router Adapter Guide - 1.4 Update 2 October 22, 1999 B-15
“TBSI Online Init the ORCAs /
xmain_dp= %x, xmain_hp= %x, len1=%d, time=%x, date=%x, data=%x"
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_cnfg.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: INFO
DESCRIPTION: Logged when the SP Switch Router Adapter card prepares to program
the FPGAs.
“TBSI-RX: TBIC's TOD: 0x%x, 0x%x.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_svc.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: INFO
DESCRIPTION: The SP Switch Router Adapter card displays the content of the TBIC’s
TOD register every time it reads it.
“TBSI-TX Unexpected SVC threshold interrupt.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: tx/tbsi_svc.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: WARNING
DESCRIPTION: This message is logged whenever the TX-CPU receives an interrupt
from the Transmit TBIC indicating that it has received a service message. No action will
need to be taken, but if the problem persists, reset the card.
“TBUS Parity Error from RC, int1=%d.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: rx/tbsi_svc.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: FATAL
DESCRIPTION: This message is logged when the RX-CPU detects that the RC has
detected a parity error on the TBUS. This is a fatal error, the card is reset and reloaded
automatically. If the problem persists, reset/replace the card. int1 is the content of the
RC’s interrupt register.
“TBUS Parity Error from TC, int1=%d.”
LOG_FILE: /var/log/gr.console
SOURCE_FILE: tx/tbsi_svc.c
SCOPE: CARD
CONTEXT: RUNNING
SEVERITY: FATAL