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PCI-6023E/6024E/6025E User Manual I-4
©
National Instruments Corporation
description (table), 4-5
general-purpose timing signal
connections, 4-47
signal summary (table), 4-8
GPCTR1_UP_DOWN signal, 4-47 to 4-49
ground-referenced signal sources
description, 4-9
differential connections, 4-14
single-ended connections
(NRSE configuration), 4-18 to 4-19
H
hardware
configuration, 2-1 to 2-2
installation, 2-2
hardware overview
analog input, 3-2 to 3-5
dither, 3-3 to 3-4
input mode, 3-2
input range, 3-2 to 3-3
analog output, 3-5
block diagram, 3-1
digital I/O, 3-6
timing signal routing, 3-6 to 3-9
board and RTSI clocks, 3-8
programmable function inputs,
3-7 to 3-8
RTSI triggers, 3-8 to 3-9
I
I/O connectors, 4-1 to 4-8
exceeding maximum ratings
(warning), 4-1
optional connectors, B-2 to B-6
50-pin E Series connector pin
assignments (figure), B-5
50-pin extended digital input
connector pin assignments
(figure), B-6
68-pin E Series connector pin
assignments (figure), B-3
68-pin extended digital input
connector pin assignments
(figure), B-4
pin assignments (table)
PCI-6023E/6024E, 4-2
PCI-6025E, 4-3
IBF signal
description (table), 4-25
mode 1 input timing (figure), 4-27
mode 2 bidirectional timing (figure), 4-29
input mode. See analog input modes.
input range, 3-2 to 3-3
exceeding common-mode input ranges
(caution), 4-10
measurement precision (table), 3-3
installation
common questions, C-2
hardware, 2-2
software, 2-1
unpacking PCI-6023E/6024E/6025E, 1-2
INTR signal
description (table), 4-26
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
L
LabVIEW and LabWindows/CVI application
software, 1-3
M
manual. See documentation.
mode 1 input timing (figure), 4-27
mode 1 output timing (figure), 4-28
mode 2 bidirectional timing (figure), 4-29
multichannel scanning considerations,
3-4 to 3-5
PCI.book Page 4 Wednesday, September 16, 1998 9:09 AM