Filter
Top Products
Chapter 4 Signal Connections
PCI-6023E/6024E/6025E User Manual 4-32
©
National Instruments Corporation
will depend upon the particular timing signal being controlled. The
detection requirements for each timing signal are listed within the section
that discusses that individual signal.
In edge-detection mode, the minimum pulse width required is 10 ns. This
applies for both rising-edge and falling-edge polarity settings. There is no
maximum pulse-width requirement in edge-detect mode.
In level-detection mode, there are no minimum or maximum pulse-width
requirements imposed by the PFIs themselves, but there may be limits
imposed by the particular timing signal being controlled. These
requirements are listed later in this chapter.
DAQ Timing Connections
The DAQ timing signals are SCANCLK, EXTSTROBE*, TRIG1, TRIG2,
STARTSCAN, CONVERT*, AIGATE, and SISOURCE.
Posttriggered data acquisition allows you to view only data that is acquired
after a trigger event is received. A typical posttriggered DAQ sequence is
shown in Figure 4-17. Pretriggered data acquisition allows you to view data
that is acquired before the trigger of interest in addition to data acquired
after the trigger. Figure 4-18 shows a typical pretriggered DAQ sequence.
The description for each signal shown in these figures is included later in
this chapter.
Figure 4-17.
Typical Posttriggered Acquisition
13042
TRIG1
STARTSCAN
CONVERT*
Scan Counter
PCI.book Page 32 Wednesday, September 16, 1998 9:09 AM