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CHAPTER 7 CLOCK GENERATOR
(2) Oscillation mode selection register (OSMS)
This register specifies whether the clock output from the main system clock oscillator without passing through
the scaler is used as the main system clock, or the clock output via the scaler is used as the main system
clock.
OSMS is set with 8-bit memory manipulation instruction.
RESET input sets OSMS to 00H.
Figure 7-4. Oscillation Mode Selection Register Format
Cautions 1. As shown in Figure 7-5 below, writing data (including same data as previous) to OSMS
cause delay of main system clock cycle up to 2/f
x during the write operation. Therefore,
if this register is written during the operation, in peripheral hardware which operates with
the main system clock, a temporary error occurs in the count clock cycle of timer, etc.
In addition, because the oscillation mode is changed by this register, the clocks for
peripheral hardware as well as that for the CPU are switched.
Therefore, writing to OSMS should be performed only immediately after reset signal
release and before peripheral hardware operation starts.
2. When writing “1” to MCS, V
DD must be 2.7 V or higher before the write execution.
Figure 7-5. Main System Clock Waveform due to Writing to OSMS
Remarks fxx : Main system clock frequency (fx or fx/2)
fx : Main system clock oscillation frequency
MCS
Main System Clock Scaler Control
0
1
Scaler used
Scaler not used
000 0OSMS FFF2H
765432Symbol
1
0MCS
0
0
Address
After
Reset
R/W
00H W
0
Write to OSMS
(MCS 0)
f
XX
Max. 2/f
X
Operating at f
XX
= f
X
/2 (MCS = 0) Operating at f
XX
= f
X
/2 (MCS = 0)