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CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
(3) Slave wait release (slave reception)
The wait status of a slave is released by setting the WREL flag, which is bit 2 of the interrupt timing specify
register (SINT), or by executing a serial I/O shift register 0 (SIO0) write instruction.
When a slave receives data, if the SCL line immediately enters a high-impedance state due to a write to
SIO0, the slave may not receive the first bit of the data sent from the master. This is because SIO0 cannot
start operation if the SCL line is in a high-impedance state during execution of a write instruction to SIO0
(until the next instruction execution is started). Therefore, manipulate the P27 output latch through the program
as shown in Figure 18-26 to receive data correctly.
For these timings, see Figure 18-22.
Figure 18-26. Slave Wait Release (Reception)
(4) Reception completion of slave
During processing of reception completion by a slave device, confirm the statuses of CMDD and COI (if
CMDD = 1). This procedure is necessary to use the wake-up function normally. If an uncertain amount of
data is sent from the master device, the slave device cannot determine whether the start condition signal or
the data will be sent from the master. This may disable use of the wake-up function.
Writing
data
to SIO0
Setting
CSIIF0
Setting
ACKD
Serial transmission
923
A0 W ACK D7 D6 D5
P27
output
latch 1
Setting
CSIIF0
ACK
output
Serial reception
Write
FFH
to SIO0
P27
output
latch 0
Wait
release
Software operation
Hardware operation
SCL
Software operation
Hardware operation
Transfer line
Master device operation
Slave device operation
1
SDA0 (SDA1)