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Table 2.12 Measurement Items (cont)
Classification Type Measurement Item Option Note
CPU
performance
(cont)
Stalled
cycle
Cycles stalled in full-
trace mode (with
multi-counts)
SFM All items are counted
independently.
Cycles stalled in full-
trace mode (without
multi-counts)
SF This item is not counted if the
stall cycle is generated
simultaneously with a stall
cycle that has occurred due
to instruction execution.
TLB
performance
TLB Number of UTLB miss
for instruction fetch
UMI The number of TLB-miss
exceptions generated by an
instruction fetch (number of
EXPEVT sets).
Number of UTLB miss
for operand fetch
UMO The number of TLB-miss
exceptions generated by an
operand access (number of
EXPEVT sets).
Number of ITLB miss IM The number of ITLB misses
for valid accesses (does not
include UTLB hits or misses).
Instruction bus
performance
Instruction Number of memory
accesses for
instruction fetch
MIF The number of memory
accesses by an instruction
fetch.
Accesses canceled by an
instruction-fetch bus are not
counted.
Instruction fetches, which
have been fetched in
anticipation of a branch but
not actually executed, are
counted.
Accesses by the PREFI
instruction are included.
Number of instruction
cache access
IC The number of accesses for
an instruction cache during
memory access of the
opcode.