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Table 2.12 Measurement Items (cont)
Classification Type Measurement Item Option Note
Operand bus
performance
(cont)
Access
count (cont)
Number of internal-
RAM access for
operand fetch
(WRITE) (XY-RAM
or L memory)
XLW The number of accesses to XY
memory in the SH7343 during
memory access (write) of an
operand.
(Accesses via the XY bus and
the operand bus are included.
When MOVX and MOVY are
executed simultaneously, it
increments one count
regardless of the read or write.)
Number of U-RAM
access (READ)
UR The number of U-memory
accesses during memory
access (read) of an operand.
(Accesses via the cache are
not included.)
Number of U-RAM
access (WRITE)
UW The number of U-memory
accesses during memory
access (write) of an operand.
(Accesses via the cache are
not included.)
Access
miss count
Number of operand
cache miss (READ)
CMR The number of cache misses
by an operand cache access
(read) (number of accesses to
the outside of the CPU core
due to a cache miss).
Cache misses are not counted
by the PREF instruction.
Number of operand
cache miss (WRITE)
CMW The number of cache misses
by an operand cache access
(write) (number of accesses to
the outside of the CPU core
due to a cache miss).
Write-through accesses are not
counted.
Cache misses are not counted
by the PREF instruction.
Number of U-RAM
read-buffer miss
UBM