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• Reset Signals
The SH7630 reset signals are only valid during emulation started with clicking the GO or STEP-
type button. If these signals are input from the user system in command input wait state, they are
not sent to the SH7630.
Note: Do not break the user program when the /RESETP and /WAIT signals are being low. A
TIMEOUT error will occur. If the /WAIT signal is fixed to low during break, a
TIMEOUT error will occur at memory access.
• Direct Memory Access Controller (DMAC)
The DMAC operates even when the emulator is used. When a data transfer request is generated,
the DMAC executes DMA transfer.
• Memory Access during User Program Execution
When a memory is accessed from the memory window, etc. during user program execution, the
user program is resumed after it has stopped in the E10A emulator to access the memory.
Therefore, realtime emulation cannot be performed.
The stopping time of the user program is as follows:
Environment:
Host computer: 650 MHz (Pentium
®
III)
SH7630: 60 MHz
JTAG clock: 3.75 MHz
When a one-byte memory is read from the command-line window, the stopping time will be about
20 ms.
• Memory Access during User Program Break
The emulator can download the program for the flash memory area. Other memory write
operations are enabled for the RAM area. Therefore, an operation such as memory write or
BREAKPOINT should be set only for the RAM area.
• Cache Operation during User Program Break
When cache is enabled, the emulator accesses the memory by the following methods:
At memory write: Writes through the cache, then writes to the memory.
At memory read: Does not change the cache write mode that has been set.
Therefore, when memory read or write is performed during user program break, the cache state
will be changed.