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Internal Trace Function: This function is activated by selecting the [Internal trace] radio button
in the [Trace type] group box of the [Trace mode] page. See figure 2.1, [Trace mode] Page. The
internal trace functions are also activated by selecting each check box on the [Branch trace] page.
Notes: 1. If an interrupt is generated at the program execution start or end, including a step
execution, the emulator address may be acquired. In such a case, the following
message will be displayed. Ignore this address because it is not a user program address.
*** EML ***
2. If a completion-type exception occurs during exception branch acquisition, the next
address to the address in which an exception occurs is acquired.
3. Trace information cannot be acquired for the following branch instructions:
• The BF and BT instructions whose displacement value is 0
• Branch to H'A0000000 by reset
4. When [User] is specified in the [UBC mode] list box in the [Configuration] window,
the internal trace is not acquired. In this case, exit the [Trace] window.
2.2.4 Notes on Using the JTAG Clock (TCK) and AUD Clock (AUDCK)
The JTAG clock (TCK) and AUD clock (AUDCK), which can be set in the [Configuration]
window, have notes as follows.
Set the JTAG clock (TCK) frequency to less than the frequency of the SH7630 peripheral module
clock (CKP).
Set the AUD clock (AUDCK) frequency 50 MHz or below for PCMCIA and PCI cards.
2.2.5 Notes on Setting the [Breakpoint] Dialog Box
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
Accordingly, it can be set only to the internal RAM area. However, a BREAKPOINT cannot
be set to the following addresses:
• An area other than CS0 to CS6 and the internal RAM
• An instruction in which Break Condition 2 is satisfied
• A slot instruction of a delayed branch instruction
3. During step execution, a BREAKPOINT is disabled.
4. Conditions set at Break Condition 2 are disabled when an instruction to which a
BREAKPOINT has been set is executed. Do not set a BREAKPOINT to an instruction in
which Break Condition 2 is satisfied.
5. When execution resumes from the address where a BREAKPOINT is specified, single-step
execution is performed at the address before execution resumes. Therefore, realtime operation
cannot be performed.