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6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
7. When a BREAKPOINT is set to the cacheable area, the cache block containing the
BREAKPOINT address is filled immediately before and after user program execution.
8. Note on DSP repeat loop:
A BREAKPOINT is equal to a branch instruction. In some DSP repeat loops, branch
instructions cannot be set. For these cases, do not set BREAKPOINTs. Refer to the hardware
manual for details.
9. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a
mark ! will be displayed in the [BP] area of the address on the [Editor] or [Disassembly]
window by refreshing the [Memory] window, etc. after Go execution. However, no break will
occur at this address. When the program halts with the break condition, the mark ! disappears.
2.2.6 Notes on Setting the [Break Condition] Dialog Box and BREAKCONDITION_SET
Command
1. Break Condition 2 is disabled during step execution.
2. Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is
executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break
Condition 2.
3. When a Break Condition is satisfied, emulation may stop after two or more instructions have
been executed.
4. If a PC break address condition is set to the slot instruction after a delayed branch instruction,
user program execution cannot be terminated before the slot instruction execution; execution
stops before the branch destination instruction.
5. Break Condition 1,2 is used as the measurement range in the performance measurement
function when [PA-1 start point] and [PA-1 end point] are displayed on the [Action] part in
the [Break condition] sheet of the [Event] window. This applies when the Break Condition is
displayed with the BREAKCONDITION_DISPLAY command in the command-line function.
In this case, a break does not occur when Break Condition 1,2 is satisfied.
6. Note that a break occurs with a break satisfaction condition by an instruction that has been
cancelled due to the generation of an exception.
7. Use the sequential break or count break with the L-bus condition. If such break is used with
the I-bus condition, it will not operate correctly.
8. A break will not occur with the execution counts specified on the execution of the multi-step
instruction.