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ELECTRICAL SPECIFICATION SSD-DXXX(I)-4300 DATA SHEET
SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
4300D-00DSR PAGE 21 FEBRUARY 27, 2009
Figure 11: Initiating a UDMA Data-Out Burst
Note: The definitions for the DIOW-:STOP, IORDY:DDMARDY-
:DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are not in
effect until DMARQ and DMACK are asserted.
Figure 12: Sustained UDMA Data-Out Burst
Note: DD(15:0) and HSTROBE signals are shown at both the device and
the host to emphasize that the cable settling time as well as cable
propagation delay does not allow the data signals to be considered stable
at the device until some time after they are driven by the host.
DMARQ
(device)
DMACK-
(
host
)
STOP
(host)
DDMARDY-
(device)
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2,
CS0-, CS1-
t
UI
t
ACK
t
ENV
t
ZIORDY
t
LI
t
DVS
t
DVH
t
ACK
t
ACK
t
UI
t
DH
t
DS
t
DVH
HSTROBE
at host
DD(15:0)
at host
HSTROBE
at device
DD(15:0)
at device
t
DVH
t
CYC
t
CYC
t
DVS
t
DVS
t
DS
t
DH
t
2CYC
t
DH
t
DVH
t
2CYC