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ATA REGISTERS SSD-DXXX(I)-4300 DATA SHEET
SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
4300D-00DSR PAGE 39 FEBRUARY 27, 2009
DEVICE ADDRESS REGISTER
The Device Address register is used to maintain compatibility with ATA disk
drive interfaces.
Table 26: Device Address Register
Operation
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Read/Write - nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0
Default Value00 111110
Bit(s) Description
7 Reserved bit.
6 Write Gate (nWTG). Low when a write to the device is in process.
5-2 nHS3 to nHS0. The negated binary address of the currently selected
head.
1 nDS1. Low when drive 1 is selected and active.
0 nDS0. Low when drive 0 is selected and active.